MB86290A Datasheet, PDF (24/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

2.3 Signal Descriptions
2.3.1 Host CPU Interface
Host CPU Interface Signals
Signal Name
MODE0-1
XRESET
D0-31
A2-A24
I/O
Input
Input
In/Out
Input
BCLKI
XBS
XCS
XRD
XWE0
XWE1
XWE2
XWE3
XRDY
Input
Input
Input
Input
Input
Input
Input
Input
Output
Tri-state
DREQ
Output
DRACK/DMAAK Input
DTACK/XTC
Input
XINT
Output
TEST0-5
Input
Description
Host CPU Mode selection
Hardware reset
Host CPU bus data
Host CPU bus address (In the V832 mode, A[24] is
connected to XMWR.)
Host CPU bus clock
Bus cycle start
Chip select
Read strobe
Write strobe for D0-D7
Write strobe for D8-D15
Write strobe for D16-D23
Write strobe for D24-D31
Wait request signal (In the SH3 mode, when this
signal is 0, it indicates the wait state; in the SH4 and
V832 modes, when this signal is 1, it indicates the wait
state.)
DMA request signal (This signal is low-active in both
the SH mode and V832 mode.)
Acknowledge signal issued in response to DMA
request (DMAAK is used in the V832 mode; this signal
is high-active in both the SH mode and V832 mode.)
DMA transfer strobe signal (XTC is used in the V832
mode. In the SH mode, this signal is high-active; in
the V832 mode, it is low-active.)
Interrupt signal issued to host CPU (In the SH mode,
this signal is low-active; in the V832 mode, it is high-
active)
Test signals
24