MB86290A Datasheet, PDF (25/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

♦ MB86290A can be connected to the Hitachi SH4 (SH7750), SH3
(SH7709/09A) and NEC V832. In the SRAM interface mode, MB86290A can
be used with any other CPU as well. The host CPU is specified by the MODE
pins.
MODE 1
L
L
H
H
MODE 2
L
H
L
H
CPU
SH3
SH4
V832
Reserved
♦ The host interface data bus is 32-bits wide (fixed).
♦ The address bus is 24-bits wide (per double word), and has a 32-
Mbyte address field. MB86290A uses a 32-Mbyte address field.
♦ The external bus frequency is up to 100 MHz.
♦ In the SH4 mode and V832 mode, when the XRDY signal is low, it is
in the ready state. In the SH3 mode, when the XRDY signal is low, it
is in the wait state.
♦ DMA data transfer is supported using an external DMAC.
♦ An interrupt request signal is generated to the host CPU.
♦ The XRESET input must be kept low (active) for at least 300 µs after
setting the S (PLL reset) signal to high.
♦ TEST signals must be clamped to high level.
♦ In the V832 mode, MB86290A signals are connected to the V832 CPU
as follows:
MB86290A Signal Pins
A24
DTACK
DRACK
V832 Signal Pins
XMWR
XTC
DMAAK
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