MB86290A Datasheet, PDF (165/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.2.5 Timing of Read/Write Access to Same Row Address
MCLKO
MRAS
MCAS
TRCD
MWE
MA
ROW
MD
COL
COL
CL
LOWD
DATA
DATA
DQM
ROW: Row Address
COL: Column Address
DATA: READ DATA
TRAS: RAS Active Time
TRCD: RAS to CAS Delay Time
CL: CAS Latency
TRP: RAS Precharge Time
LOWD: Last Output to Write Command Delay
Note: This timing is used when
CL2 is operating.
Fig. 8.2.5 Timing of Read/Write Access to Same Row Address
This timing diagram shows that a row address of SDRAM is read-accessed
from the MB86290A, and then immediately afterwards the same row address
is write-accessed from the MB86290A. The Write command is issued after
LOWD has elapsed after read data is output from SDRAM.
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