MB86290A Datasheet, PDF (156/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.1.7 SH3/4 Dual-Address DMA (Transfer of 8 Long Words)
For the MB86290A, the read/write operation is performed according to the SRAM protocol.
BCLKIN
DREQ
A[24:2]
D[31:0]
Source address
• c• •c c
Read 1
Read 2 _{• c• •c c} Read 8
• c• •c c
Destination address
• c• c• c
Write 1
Write 2 _{• c• c• c} Write 8
• c• c• c
Fig. 8.7 SH3/4 Dual-address DMA (Transfer of 8 Long Words)
In the dual-address mode, the DREQ signal is kept asserted until the
transfer ends by default. Consequently, to negate the DREQ signal when the
MB86290A cannot return the Ready signal immediately, set the DBM
register.
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