MB86290A Datasheet, PDF (54/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

5.6 Synchronization Control
5.6.1 Applicable Display Resolution
The following table shows typical display resolutions and their sync signal
frequencies. The pixel clock frequency is determined by setting the division
rate of the display reference clock. The display reference clock is either the
internal PLL (200.45452 MHz at input frequency of 14.31818 MHz), or the
clock supplied to the DCLKI input pin. The following table gives the clock
division rate used when the internal PLL is the display reference clock:
Resolution
320 × 240
400 × 240
480 × 240
640 × 480
854 × 480
800 × 600
1024 × 768
Division
rate of
reference
clock
1/30
1/24
1/20
1/8
1/6
1/5
1/3
Pixel
frequency
Horizontal
total pixel
count
Horizontal
frequency
Vertical
total raster
count
Vertical
frequency
6.7 MHz
8.4 MHz
10.0 MHz
25.1 MHz
33.4 MHz
40.1 MHz
66.8 MHz
424
15.76 kHz
263
530
15.76 kHz
263
636
15.76 kHz
263
800
31.5 kHz
525
1062
31.3 kHz
525
1056
38.0 kHz
633
1389
48.1 kHz
806
59.9 Hz
59.9 Hz
59.9 Hz
59.7 Hz
59.9 Hz
60.0 Hz
59.9 Hz
Pixel frequency = 14.31818 MHz × 14 x reference clock division rate (when
internal PLL selected)
= DCLKI input frequency × reference clock division rate (when DCLKI
selected)
Horizontal frequency = Pixel frequency/Horizontal total pixel count
Vertical frequency = Horizontal frequency/Vertical total raster count
5.6.2 Interlace Display
The MB86290A can generate both a non-interlace display and an interlace
display. For the interlace display, the 1st, 3rd, … (2n+1)th rasters of the
display screen are output to odd fields, and 2nd, 4th, … 2n-th rasters of the
display screen are output to even fields.
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