MB86290A Datasheet, PDF (94/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

7.1.1 Host Interface Registers
DTC (DMA Transfer Count)
Register address
HostBaseAddress + 00h
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
R0
0
DTC
RW
Don’t care
DTCR is a 32-bit wide register to set the DMA data transfer count to either
one long-word (32 bits) or eight long-word (32 bytes) units. This register is
read/write enabled. When 1h is set, one data unit is transferred by DMA.
However, when 0h is set, it indicates the maximum transfer data count and
16M (16,777,216) data units are transferred. After DMA transfer is started,
the register value cannot be overwritten until DMA transfer is completed.
Note: In the V832 mode, no setting is required for this register.
DSU (DMA Set Up)
Register address ^{HostBaseAddress + 04h}
7
Bit #
Bit field name
R/W
Default
6
5
4
Reserved
R0
0
3
2
1
0
DAM
DBM
DW
RW
RW
RW
0
0
0
Bit0 DW(DMA Word)
Sets DMA transfer unit
0 1 long words (32 bytes) per DMA transaction
1 8 long word (32 bits) per DMA transaction (only SH4)
Bit1 _{DBM (DMA Bus request Mode)}
Selects DREQ mode used when performing DMA transfer in dual-address mode
0 DREQ is irrelevant to the cycle steal mode or burst mode, and is not negated during DMA transfer.
1 DREQ is irrelevant to the cycle steal mode or burst mode, and is negated when the MB86290A cannot
receive data (that is, when Ready cannot be returned immediately). When the MB86290A is ready to
receive data, DREQ is reasserted (When DMA transfer is performed in the single-address mode,
DREQ is controlled automatically).
Bit2 DAM(DMA Address Mode)
Sets DMA addressing mode
0 Dual address mode
1 Single address mode (SH4 only)
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