MB86290A Datasheet, PDF (31/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

3.2 Access Mode
3.2.1 SRAM Interface
Data can be transferred to/from MB86290A using a typical SRAM access
protocol. MB86290A internal registers, internal memory and external
memory are all mapped to the physical address field of the host CPU. The
host CPU can access any of them like a normal memory device. Since
MB86290A uses a hardware wait using the XRDY signal output, the
respective hardware wait option of the host CPU must be enabled.
CPU Read
The host CPU reads data from internal registers and memory of MB86290A
in double-word (32 bit) units.
CPU Write
The host CPU writes data to internal registers and memory of MB86290A in
byte units.
3.2.2 FIFO Interface
This interface transfers display lists in host memory. Display list information
is transferred efficiently by using a single address mode DMA operation. This
FIFO is mapped to the physical address field of the host CPU so that the
same data transfer can be performed in either the SRAM mode or dual
address DMA mode by specifying the FIFO in the destination address.
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