MB86290A Datasheet, PDF (161/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.2 Graphics Memory Interface
The access timing for the MB86290A and the graphics memory is explained.
8.2.1 Timing of Read Access to Same Row Address
MCLKO
MRAS
MCAS
TRCD
MWE
MA
ROW
MD
COL
COL
COL
COL
CL
DATA DATA DATA DATA
DQM
ROW: Row Address
COL: Column Address
DATA: READ DATA
TRCD: RAS to CAS Delay Time
CL: CAS Latency
Note: This timing is used when CL2 is
operating.
Fig. 8.2.1 Timing of Read Access to Same Row Address
This timing diagram shows that the same row address of SDRAM is read-
accessed four times from the MB86290A. The Read command is issued after
TRCD has elapsed after the ACTV command was issued.
Data that is output after CL has elapsed after the Read command was issued
is written to the MB86290A.
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