MB86290A Datasheet, PDF (29/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

2.3.4 Clock Input
Signal Name
I/O
CLK
Input
Clock Input Signals
Description
Clock input signal
S
Input
PLL reset signal
CKM
Input
Clock mode signal
♦ Inputs source clock for generating internal operation clock and
display dot clock. Normally, 4 Fsc(= 14.31818 MHz) is input. An
internal PLL generates the internal operation clock of 100.22726 MHz
and the display base clock of 200.45452 MHz.
♦ For the internal operation clock, use either the output clock of the
internal PLL (x7 of input clock) or the bus clock input (BCLK1) from
the host CPU. When the host CPU bus speed is 100 MHz, the BCLK1
input should be selected.
CKM
L
H
Clock mode
Output from internal PLL selected
Host CPU bus clock (BCLK1) selected
♦ At power-on, a low-level signal must be input to the S-signal pin for
more than 500 ns and then set to high. After the S-signal input is
set to high, a low-level signal must be input to XRESET for another
300 µs.
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