MB86290A Datasheet, PDF (103/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

HTP (Horizontal Total Pixels)
Register address ^{DisplayBaseAddress + 06h}
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name
Reserved
HTP
R/W
R0
RW
Default
0
Don’t care
This register controls the total pixel count. Setting + 1 is the total pixel
count.
HDP (Horizontal Display Period)
DisplayBaseAddress + 08h
Register address
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name
Reserved
HDP
R/W
R0
RW
Default
0
Don’t care
This register controls the total horizontal display period in pixel clock units.
Setting + 1 is the pixel count for the display period.
HDB (Horizontal Display Boundary)
DisplayBaseAddress + 0Ah
Register address
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name
Reserved
HDB
R/W
R0
RW
Default
0
Don’t care
This register controls the display period of the left partition in pixel raster
units Setting + 1 is the pixel count for the display period of the left partition.
When the screen is not partitioned into right and left before display, set the
same value as HDP.
HSP (Horizontal Synchronize pulse Position)
DisplayBaseAddress + 0Ch
Register address
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name
Reserved
HSP
R/W
R0
RW
Default
0
Don’t care
This register controls the HSYNC pulse position in pixel clock unit. When
the clock count since the start of the display period reaches Setting + 1, the
horizontal synchronization signal is asserted.
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