MB86290A Datasheet, PDF (97/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

IMASK (Interrupt MASK)
Register address ^{HostBaseAddress + 24h}
7
Bit #
Bit field name
R/W
Default
6
Reserved
R0
0
5
4
3
2
1
0
SYNCERRM
RW
0
FSYNCM
RW
0
VSYNCM
RW
0
CENDM
RW
0
CERRM
RW
0
This register masks interrupt requests. When the flag is set to 1, the
respective event is masked so that no interrupt request is asserted to the
host CPU when an event occurs.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
CERRM (Command Error Interrupt Mask)
Masks draw command execution error interrupt
CENDM (Command Interrupt Mask)
Masks draw command complete interrupt
VSYNCM (Vertical Sync. Interrupt Mask)
Masks VSYNC detection interrupt
FSYNCM (Frame Sync. Interrupt Mask)
Masks frame synchronization interrupt
SYNCERRM (Sync. Error Interrupt Mask)
Masks external synchronization error interrupt
SRST (Software ReSeT)
HostBaseAddress + 2Ch
Register address
Bit #
7
6
Bit field name
R/W
Default
5
4
3
Reserved
R0
0
2
1
0
SRST
W1
0
This register controls software reset. When 1 is set at this register, a
software reset is issued.
LSA (displayList Source Address)
HostBaseAddress + 40h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
R0
0
LSA
RW
R0
Don’t care
0
This register sets the DisplayList transfer source address. When DisplayList
is transferred from Graphics Memory, set the List start address. Since the
lowest two bits of this register are always set to 0, DisplayList must be 4-byte
aligned. The contents set at this register do not change until another value
is set.
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