MB86290A Datasheet, PDF (160/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.1.11 V832 DMA Transfer End Timing
For the MB86290A, the read/write operation is performed according to the SRAM protocol.
BCLKIN
DMARQ
A[24:2]
D[31:0]
Source address
Read
Destination address
Write
DMAAK
XTC
Fig. 8.11 V832 DMA Transfer End Timing
DMMAK and XTC are ANDed inside the MB86290A to end DMA.
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