MB86290A Datasheet, PDF (34/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

3.3.5 Ending DMA Transfer
♦ SH3/SH4
When the MB86290A transfer count register is set to 0, DMA transfer
ends and DREQ is negated.
♦ V832
When the XTC signal from the CPU is low-asserted while the DMAAK
signal to MB86290A is high-asserted, the end of DMA transfer is
recognized and DREQ is negated.
The end of DMA transfer is detected in two ways: the DMA status register
(DST) is polled, and an interrupt to end the drawing command (FD000000h)
is added to the display list and the interrupt is detected.
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