MB86290A Datasheet, PDF (121/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

CTC (C-layer Transparent Control)
Register address ^{DisplayBaseAddress + BCh}
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name CZT
CTC
R/W
RW
RW
Default
0
Don’t care
This register controls the transparent color setting for the C layer. The color
defined as a transparent color by this register is treated as a transparent
color even in the blending mode. When both CTC and CZT are set to 0, color
0 is displayed in black (not transparent).
Bits 14-0 CTC (C-layer Transparent Color)
Set color code of transparent color used in Console layer. Bits 7-0 used in indirect color mode.
Bit 15
CZT (C-layer Zero Transparency)
Sets treatment for code 0 in Console layer
0
Code 0 not transparent color
1
Code 0 transparent color
MRTC (MR-layer Transparent Control)
Register address ^{DisplayBaseAddress + C0h}
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name MRZT
MRTC
R/W
RW
RW
Default
0
Don’t care
This register controls the transparent color setting for the MR-layer. When
both MRTC and MRZT are set to 0, color 0 is displayed in black (not
transparent).
Bits 14-0 MRTC (MR-layer Transparent Color)
Set color code of transparent color used in MR-layer. Bits 7-0 used in indirect color mode.
Bit 15
MRZT (MR-layer Zero Transparency)
Sets treatment for code 0 in MR-layer
0
Code 0 not transparent color
1
Code 0 transparent color
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