MB86290A Datasheet, PDF (168/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.3 Display Timing
8.3.1 Non-interlaced Video Mode
AOUTx
HSYNC
VSYNC
VTR+1 rasters
VSP+1 rasters
VDP+1 rasters
VSW+1 rasters
Assert Frame Interrupt
Assert Vsync Interrupt
AOUTx
HSYNC
HDP+1 clocks
HSP+1 clocks
HTP+1 clocks
HSW+1 clocks
In the above diagram, VTR, HDP, etc., are the settings of their associated
registers.
The VSYNC/frame interrupt is asserted when display of the last raster ends.
When updating display parameters, synchronize with the frame interrupt so
no display disturbance occurs. Calculation for the next frame is started
immediately after the vertical synchronization pulse is asserted, so the
parameters must be updated by the time that calculation is started.
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