MB86290A Datasheet, PDF (176/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

9.4.2 Video Interface
Clock
Parameter
CLK Frequency
CLK H-width
CLK L-width
DCLKI Frequency
DCLKI H-width
DCLKI L-width
DCLKO frequency
Symbol
fCLK
tHCLK
tLCLK
fDCLKI
tHDCLKI
tLDCLKI
fDCLKO
Condition
Specifications
Min.
Typ.
Max.
14.32
25
25
67
5
5
67
Unit
MHz
ns
ns
MHz
ns
ns
MHz
Input signals
Parameter
HSYNC Input pulse width
HSYNC Input set up time
HSYNC Input hold time
VSYNC Input pulse width
EO Input set up time
EO Input hold time
Symbol
tWHSYNC0
tWHSYNC1
tSHSYNC
tHHSYNC
tWHSYNC1
tSEO
tHEO
Condition
*1
*2
*2
*2
*3
*3
Specifications
Min.
Typ.
Max.
3
3
10
10
1
10
10
Unit
clock
clock
ns
ns
HSYNC
period
ns
ns
*1 In PLL synchronization mode (CKS = 0), base clock output from internal PLL (period = 1/14*fCLK)
*2 In DCLKI synchronization mode (CKS = 1), base clock = DCLKI
*3 For VSYNC negation edge
Output signals
Parameter
EO Output delay time
HSYNC Output delay time
VSYNC Output delay time
CSYNC Output delay time
GV Output delay time
Specifications
Symbol
Condition
Unit
Min.
Typ.
Max.
tDEO
*4
10
ns
tDHSYNC
10
ns
tDVSYNC
10
ns
tDCSYNC
10
ns
tDGV
10
ns
*4 EO output changes at timing of VSYNC assertion
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