MB86290A Datasheet, PDF (113/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

BLOA0 (BL-layer Origin Address 0)
DisplayBaseAddress + 74h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
BLOA0
RW
Don’t care
R0
0000
This register controls the base address of the logical frame (frame0) of the
Base Left (BL) layer. Since the lowest 4 bits are fixed to 0, this address is 16-
byte aligned.
BLDA0 (BL-layer Display Address 0)
DisplayBaseAddress + 78h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
BLDA0
RW
Don’t care
This register controls the base address of the Base Left (BL) layer display field
in frame0. When the direct color mode is used, the LSB is fixed to 0 and this
address is 2-byte aligned.
BLOA1 (BL-layer Origin Address 1)
DisplayBaseAddress + 7Ch
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
BLOA1
RW
Don’t care
R0
0000
This register controls the base address of the logical frame (frame1) of the
Base Left (BL) layer. Since the lowest 4 bits are fixed to 0, this address is 16-
byte aligned.
BLDA1 (BL-layer Display Address 1)
DisplayBaseAddress + 80h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
BLDA1
RW
Don’t care
This register controls the base address of the Base Left (BL) layer display field
in frame1. When the direct color mode is used, the LSB is fixed to 0 and this
address is 2-byte aligned.
BLDX (BL-layer Display position X)
DisplayBaseAddress + 84h
Register address
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit field name
Reserved
BLDX
R/W
R0
RW
Default
0
Don’t care
113