MB86290A Datasheet, PDF (152/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.1.3 CPU Read/Write Timing Diagram in V832 Mode
BCYST
A[23:2]
CS
BS
MRD(IORD
D[31:0]
MWR(IOWR)
xxBEN[3:0]
D[31:0]
READY
Hi-Z
T1 Twh1 Twh2 T2
Valid Data
Not-ready
Valid Data
Hi-Z
Not-ready Ready Not-ready Ready
{: READY sampling in V832 mode
T1: Read/write start cycle (READY is in the not-ready state.)
Twh*: Cycles inserted by hardware (READY asserts Ready as soon as the preparations are
made.)
T2: Read/write end cycle (READY is in the not-ready state.)
READY is placed in the ready state and then set to Hi-Z.
Note: The xxBEN signal is used only when performing a write from the CPU; it is not used
when performing a read from the CPU.
Fig. 8.3 CPU Read/Write Timing Diagram in V832 Mode
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