MB86290A Datasheet, PDF (117/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

CPM (Cursor Priority Mode)
Register address ^{DisplayBaseAddress + A2h}
Bit #
Bit field name
R/W
Default
7
6
Reserved
R0
0
5
CEN1
RW
0
4
CEN0
RW
0
3
2
Reserved
R0
0
1
CUO1
RW
0
This register controls the display priority of cursors. Cursor 0 is always
prioritized to cursor 1.
Bit 0
CUO0 (Cursor Overlap 0)
Sets display priority between cursor 0 and pixels of Console layer
0
Put cursor 0 at bottom of Console layer.
1
Put cursor 0 at top of Console layer.
0
CUO0
RW
0
Bit 1
CUO1 (Cursor Overlap 1)
Sets display priority between cursor 1 and pixels of Console layer
0
Put cursor 1 at bottom of Console layer.
1
Put cursor 1 at top of Console layer.
Bit 4
CEN0 (Cursor Enable 0)
Sets display enable of cursor 0
0
Disable
1
Enable
Bit 5
CEN1 (Cursor Enable 1)
Sets display enable of cursor 1
0
Disable
1
Enable
CUOA0 (Cursor-0 Origin Address)
DisplayBaseAddress + A4h
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve
R0
0
CUOA0
RW
Don’t care
R0
0000
This register controls the start address of the cursor-0 pattern. Since the
lowest 4 bits are fixed to 0, this address is 16-byte aligned.
117