MB86290A Datasheet, PDF (104/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

HSW (Horizontal Synchronize pulse Width)
Register address ^{DisplayBaseAddress + 0Eh}
Bit #
7
6
5
4
3
2
1
Bit field name
Reserved
HSW
R/W
R0
RW
Default
0
Don’t care
This register controls the HSYNC pulse width in pixel-clock units. Setting +
1 is the pulse width clock count.
VSW (Vertical Synchronize pulse Width)
DisplayBaseAddress + 0Fh
Register address
Bit #
7
6
5
4
3
2
1
Bit field name
Reserved
VSW
R/W
R0
RW
Default
0
Don’t care
This register controls the VSYNC pulse width in raster units. Setting + 1 is
the pulse width raster count.
VTR (Vertical Total Rasters)
DisplayBaseAddress + 12h
Register address
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Bit field name
Reserved
VTR
R/W
R0
RW
Default
0
Don’t care
This register controls the total raster count. Setting + 1 is the total raster
count. For the interlace display, Setting + 1.5 is the total raster count for 1
field; 2 × setting + 3 is the total raster count for 1 frame (see Section 8.3.2).
VSP (Vertical Synchronize pulse Position)
DisplayBaseAddress + 14h
Register address
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Bit field name
Reserved
VSP
R/W
R0
RW
Default
0
Don’t care
This register controls the VSYNC pulse position in raster units. The vertical
synchronization pulse is asserted starting at the Setting + 1-th raster relative
to the display start raster.
0
0
1
0
1
0
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