MB86290A Datasheet, PDF (137/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

TIS (Tile Size)
Register address ^{DrawBaseAddress + 468h}
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TISN
RW
1000000
TISM
RW
1000000
This register controls the tile size (m, n).
Bits 6-0
TISM (Title Size M)
Set horizontal tile pattern size. Any power of 2 between 4 and 64 can be used. Values that are not a
power of 2 cannot be used.
0.000100
M=4
0001000
M=8
0010000
M=16
0100000
M=32
1000000
M=64
Others
Prohibited
Bits 22-16
TISN (Title Size N)
Set vertical tile pattern size. Any power of 2 between 4 and 643 can be used. Values that are not a
power of 2 cannot be used.
0000100
N=4
0001000
N=8
0010000
N=16
0100000
N=32
1000000
N=64
Others
Prohibited
TOA (Texture Buffer Offset address)
DrawBaseAddress + 46Ch
Register address
Bit #
Bit field name
R/W
Default
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XBO
RW
Don’t care
This register controls the texture buffer offset address of. By using this offset
value, multiple texture patterns can be used and referred to the texture
buffer memory.
Specify the word-aligned byte address (16 bits). (Bit 0 is always 0.)
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