MB86290A Datasheet, PDF (171/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

8.6 SH4 Mode
(1) When the RDY pin is low, it is in the ready state.
(2) At DMA transfer in the single-address mode, transfer from the main memory (SH-mode memory) to FIFO
of the MB86290A can be performed, but transfer from the MB86290A to the main memory cannot be
performed.
(3) DMA transfer in the single-address mode is performed in units of 32 bits or 32 bytes.
(4) SH4-mode 32-byte DMA transfer in the dual-address mode supports inter-memory transfer, but does not
support transfer from memory to FIFO.
(5) The INT signal is low active.
8.7 V832 Mode
(1) When the RDY pin is low, it is in the ready state.
(2) Set the active level of DMAAK to high-active in V832 mode.
(3) DMA transfer supports the single transfer mode and demand transfer mode.
(4) The INT signal is high-active. Set the V832-mode registers to high-level trigger.
8.8 DMA Transfer Modes Supported by SH3, SH4, and V832
SH3
SH4
V832
Table 8-1 Table of DMA Transfer Modes supported by SH3, SH4, and V832
Single-address mode
Dual-address mode
SH 3 does not support the single-
address mode.
SH3 supports the direct address transfer mode; it does
not support the indirect address transfer mode.
Transfer is performed in 32-bit units.
SH3 supports the cycle steal mode and burst mode.
Transfer is performed in units of 32
bits or 32 bytes.
SH4 supports the cycle steal mode
and burst mode.
Transfer is performed in 32-bit units. Transfer to memory
is performed in 32-byte units. SH4 supports transfer to
FIFO. SH4 supports the cycle steal mode and burst
mode.
Transfer is performed in 32-bit units.
V832 supports the single transfer mode and demand
transfer mode.
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