MB86290A Datasheet, PDF (101/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

7.1.3 Display Control Register
DCM (Display Control Mode)
Register address ^{DisplayBaseAddress + 00h}
Bit #
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Bit field name CKS Reserve
SC
Reserve
EO Reserve SOF ESY
R/W
RW
R0
RW
R0
RW R0 RW RW
Default
0
00
11110
00
0
0
0
0
This register controls the display mode. It is not initialized by a software
reset.
1
0
SYNC
RW
00
Bits 1-0
SYNC (Synchronize)
Set synchronization mode
X0 Non-interlace mode
11 Interlace video mode
Bit 2
ESY (External Synchronize)
Sets external synchronization mode
0
Disable
1
Enable
Bit 3
SF (Synchronize signal output format)
Sets active level of synchronization (VSYNC, HSYNC, CSYNC) signals
0
Low active
1
High active
Bit 5
EO (Even/Odd signal mode)
Defines EO signal output format
0
Low level output at even frame, High level output at odd frame
1
High level output at even frame, Low level output at odd frame
Bits 12-8
SC (Scaling)
Define pre-scaling ratio to generate dot clock
00000
No pre-scaling
00001
1/2
00010
1/3
:
:
11110
1/31 (default)
11111
1/32
Bit 15
CKS (Clock Source)
Selects source clock
0
Internal PLL output clock
1
DCLKI input
101