MB86290A Datasheet, PDF (170/184 Pages) Fujitsu Component Limited. – Graphics Controller Hardware Specifications

Cautions
8.4 CPU Cautions
(1) Enable the hardware wait for the areas to which the MB86290A is linked. Set the software
wait count to 1.
(2) When starting DMA by issuing an external request, do so after setting the transfer count
register (DTCR) and mode setting register (DSUR) of the MB86290A to the same value as
the CPU setting. In the V832 mode, there is no need to set DTCR.
(3) When MB86290A is read-/write-accessed from the CPU during DMA transfer, do not access
the registers and memories related to DMA transfer. If these registers and memories are
accessed, reading and writing of the correct value is not assured.
(4) In the SH mode, only the lowers 32 Mbytes are used (A[25] is not used), so do not access
the uppers 32 Mbytes. When linking other devices to the uppers 32 Mbytes, create Chip
Select for the MB86290A by using glue logic.
(5) Set DREQ (DMARQ) to detection.
(6) Set the SH-mode DACK/DRACK to high active output, V832-mode DMAAK to high active,
and V832-mode TC to low active.
8.5 SH3 Mode
(1) When the RDY pin is low, it is in the wait state.
(2) DMA transfer in the single-address mode is not supported.
(3) DMA transfer in the dual-address mode supports the direct address transfer mode, but does
not support the indirect address transfer mode.
(4) 16-byte DMA transfer in the dual-address mode is not supported.
(5) The INT signal is low active.
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