MC68HC08GZ32 Datasheet, PDF (76/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Computer Operating Properly (COP) Module
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held at V_TST. During the break state,
V_TST on the RST pin disables the COP.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
6.3 I/O Signals
The following paragraphs describe the signals shown in Figure 6-1.
6.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
6.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) clears the COP counter and clears stages 12–5
of the SIM counter. Reading the COP control register returns the low byte of the reset vector. See
6.4 COP Control Register.
6.3.4 Power-On Reset
The power-on reset (POR) circuit clears the SIM counter 4096 CGMXCLK cycles after power-up.
6.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
6.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See
Chapter 5 Mask Options.
6.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See
Chapter 5 Mask Options.
MC68HC08GZ32 Data Sheet, Rev. 3
76
Freescale Semiconductor