MC68HC08GZ32 Datasheet, PDF (136/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN08 Controller (MSCAN08)
12.13.2 MSCAN08 Module Control Register 1
Address:
Read:
Write:
Reset:
$0501
Bit 7
6
5
4
3
2
1
0
0
0
0
0
LOOPB WUPM
0
0
0
0
0
0
0
= Unimplemented
Figure 12-17. Module Control Register (CMCR1)
Bit 0
CLKSRC
0
LOOPB — Loop Back Self-Test Mode
When this bit is set, the MSCAN08 performs an internal loop back which can be used for self-test
operation: the bit stream output of the transmitter is fed back to the receiver internally. The CAN_RX
input pin is ignored and the CAN_TX output goes to the recessive state (logic 1). The MSCAN08
behaves as it does normally when transmitting and treats its own transmitted message as a message
received from a remote node. In this state the MSCAN08 ignores the bit sent during the ACK slot of
the CAN frame Acknowledge field to insure proper reception of its own message. Both transmit and
receive interrupts are generated.
1 = Activate loop back self-test mode
0 = Normal operation
WUPM — Wakeup Mode
This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from
spurious wakeups (see 12.8.5 Programmable Wakeup Function).
1 = MSCAN08 will wakeup the CPU only in cases of a dominant pulse on the bus which has a length
of at least t_wup.
0 = MSCAN08 will wakeup the CPU after any recessive-to-dominant edge on the CAN bus.
CLKSRC — Clock Source
This flag defines which clock source the MSCAN08 module is driven from (see 12.10 Clock System).
1 = The MSCAN08 clock source is CGMOUT (see Figure 12-8).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 12-8).
NOTE
The CMCR1 register can be written only if the SFTRES bit in the MSCAN08
module control register is set
12.13.3 MSCAN08 Bus Timing Register 0
Address:
Read:
Write:
Reset:
$0502
Bit 7
6
5
4
3
2
1
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
0
0
0
0
0
0
0
Figure 12-18. Bus Timing Register 0 (CBTR0)
Bit 0
BRP0
0
MC68HC08GZ32 Data Sheet, Rev. 3
136
Freescale Semiconductor