MC68HC08GZ32 Datasheet, PDF(254/320 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC08GZ32 Datasheet, PDF (254/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Timer Interface Module (TIM1)

TOVx â Toggle-On-Overflow Bit

When channel x is an output compare channel, this read/write bit controls the behavior of the channel

x output when the TIM1 counter overflows. When channel x is an input capture channel, TOVx has no

effect. Reset clears the TOVx bit.

1 = Channel x pin toggles on TIM1 counter overflow.

0 = Channel x pin does not toggle on TIM1 counter overflow.

NOTE

When TOVx is set, a TIM1 counter overflow takes precedence over a

channel x output compare if both occur at the same time.

CHxMAX â Channel x Maximum Duty Cycle Bit

When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered

PWM signals to 100%. As Figure 18-9 shows, the CHxMAX bit takes effect in the cycle after it is set

or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.

NOTE

The 100% PWM duty cycle is defined as a continuous high level if the PWM

polarity is 1 and a continuous low level if the PWM polarity is 0. Conversely,

a 0% PWM duty cycle is defined as a continuous low level if the PWM

polarity is 1 and a continuous high level if the PWM polarity is 0.

OVERFLOW

OVERFLOW

PERIOD

TCHx

OVERFLOW

OVERFLOW

OVERFLOW

CHxMAX

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

Figure 18-9. CHxMAX Latency

18.9.5 TIM1 Channel Registers

These read/write registers contain the captured TIM1 counter value of the input capture function or the

output compare value of the output compare function. The state of the TIM1 channel registers after reset

is unknown.

In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM1 channel x registers

(T1CHxH) inhibits input captures until the low byte (T1CHxL) is read.

In output compare mode (MSxB:MSxA â 0:0), writing to the high byte of the TIM1 channel x registers

(T1CHxH) inhibits output compares until the low byte (T1CHxL) is written.

MC68HC08GZ32 Data Sheet, Rev. 3

254

Freescale Semiconductor

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