MC68HC08GZ32 Datasheet, PDF (246/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM1)
As Figure 18-4 shows, the output compare value in the TIM1 channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM1
to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the
TIM1 to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1).
The value in the TIM1 counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM1 counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is 000. See 18.9.1 TIM1 Status and Control Register.
The value in the TIM1 channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM1 channel registers
produces a duty cycle of 128/256 or 50%.
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
TCHx
PULSE
WIDTH
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 18-4. PWM Period and Pulse Width
OUTPUT
COMPARE
18.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 18.4.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM1 channel registers.
An unsynchronized write to the TIM1 channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a TIM1 overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The TIM1 may pass the new value before it is written to the timer channel
(T1CHxH:T1CHxL) registers.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
• When changing to a longer pulse width, enable TIM1 overflow interrupts and write the new value
in the TIM1 overflow interrupt routine. The TIM1 overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current
pulse) could cause two output compares to occur in the same PWM period.
MC68HC08GZ32 Data Sheet, Rev. 3
246
Freescale Semiconductor