MC68HC08GZ32 Datasheet, PDF(73/320 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC08GZ32 Datasheet, PDF (73/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

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5.4 Mask Option Register 1 (MOR1)

Mask Option Register 1 (MOR1)

Address:

Read:

$001F

Bit 7

COPRS

6

5

4

3

LVISTOP LVIRSTD LVIPWRD LVI5OR3

2

SSREC

1

STOP

Write:

Reset:

= Unimplemented

Unaffected by reset

Figure 5-2. Mask Option Register 1 (MOR1)

Bit 0

COPD

COPRS â COP Rate Select Bit

COPRS selects the COP timeout period. See Chapter 6 Computer Operating Properly (COP) Module.

1 = COP timeout period = 8176 COPCLK cycles

0 = COP timeout period = 262,128 COPCLK cycles

LVISTOP â LVI Enable in Stop Mode Bit

When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.

1 = LVI enabled during stop mode

0 = LVI disabled during stop mode

LVIRSTD â LVI Reset Disable Bit

LVIRSTD disables the reset signal from the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI).

1 = LVI module resets disabled

0 = LVI module resets enabled

LVIPWRD â LVI Power Disable Bit

LVIPWRD disables the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI).

1 = LVI module power disabled

0 = LVI module power enabled

LVI5OR3 â LVI 5-V or 3-V Operating Mode Bit

LVI5OR3 selects the voltage operating mode of the LVI module (see Chapter 11 Low-Voltage Inhibit

(LVI)). The voltage mode selected for the LVI should match the operating VDD (see Chapter 21

Electrical Specifications) for the LVIâs voltage trip points for each of the modes.

1 = LVI operates in 5-V mode

0 = LVI operates in 3-V mode

SSREC â Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a

4096-CGMXCLK cycle delay.

1 = Stop mode recovery after 32 CGMXCLK cycles

0 = Stop mode recovery after 4096 CGMXCLK cycles

NOTE

Exiting stop mode by an LVI reset will result in the long stop recovery.

If the system clock source selected is an external crystal and the OSCENINSTOP bit is not set, the

oscillator will be disabled during stop mode. The short stop recovery does not provide enough time for

oscillator stabilization and for this reason the SSREC bit should not be set.

MC68HC08GZ32 Data Sheet, Rev. 3

Freescale Semiconductor

73

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