MC68HC08GZ32 Datasheet, PDF (282/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Development Support
20.2.2.4 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset: 0
R = Reserved
Figure 20-8. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
20.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled,
the break module will remain enabled in wait and stop modes. However, since the internal address bus
does not increment in these modes, a break interrupt will never be triggered.
20.3 Monitor Module (MON)
The monitor module allows complete testing of the microcontroller unit (MCU) through a single-wire
interface with a host computer.
Features of the monitor module include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor read-only memory (ROM) and host
computer
• Standard mark/space non-return-to-zero (NRZ) communication with host computer
• Standard communication baud rate (7200 @ 8-MHz bus frequency)
• Execution of code in random-access memory (RAM) or FLASH
• ROM memory security feature⁽¹⁾
• 352 bytes monitor ROM code size ($FE20 to $FF7F)
• Monitor mode entry if V_TST is applied to IRQ
1. No security feature is absolutely secure. However, Freescale Semiconductor’s strategy is to make reading or copying the ROM
difficult for unauthorized users.
MC68HC08GZ32 Data Sheet, Rev. 3
282
Freescale Semiconductor