MC68HC08GZ32 Datasheet, PDF (133/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmer’s Model of Control Registers
12.12.4 Data Segment Registers (DSRn)
The eight data segment registers contain the data to be transmitted or received. The number of bytes to
be transmitted or being received is determined by the data length code in the corresponding DLR.
12.12.5 Transmit Buffer Priority Registers
Address:
Read:
Write:
Reset:
$05bD
Bit 7
6
5
4
3
2
1
PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1
Unaffected by reset
Figure 12-14. Transmit Buffer Priority Register (TBPR)
Bit 0
PRIO0
PRIO7–PRIO0 — Local Priority
This field defines the local priority of the associated message buffer. The local priority is used for the
internal prioritization process of the MSCAN08 and is defined to be highest for the smallest binary
number. The MSCAN08 implements the following internal prioritization mechanism:
• All transmission buffers with a cleared TXE flag participate in the prioritization right before the SOF
is sent.
• The transmission buffer with the lowest local priority field wins the prioritization.
• In case more than one buffer has the same lowest priority, the message buffer with the lower index
number wins.
12.13 Programmer’s Model of Control Registers
The programmer’s model has been laid out for maximum simplicity and efficiency. Figure 12-15 gives an
overview on the control register block of the MSCAN08.
Addr.
$0500
$0501
$0502
$0503
$0504
Register
Bit 7
6
Read:
0
0
CMCR0
Write:
5
4
3
2
1
0
SYNCH
SLPAK
TLNKEN
SLPRQ
Read:
0
0
0
0
0
CMCR1
LOOPB WUPM
Write:
Read:
CBTR0
Write:
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
Read:
CBTR1
SAMP
Write:
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11
Read:
CRFLG
WUPIF
Write:
RWRNIF TWRNIF RERRIF
TERRIF
BOFFIF
OVRIF
= Unimplemented
R
= Reserved
Figure 12-15. MSCAN08 Control Register Structure
Bit 0
SFTRES
CLKSRC
BRP0
TSEG10
RXF
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
133