MC68HC08GZ32 Datasheet, PDF (188/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 14-14. Flag Clearing Sequence
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an ESCI
error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with
FE set and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the ESCI detects a parity error in incoming data. PE generates
a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
14.8.5 ESCI Status Register 2
ESCI status register 2 (SCS2) contains flags to signal these conditions:
• Break character detected
• Incoming data
MC68HC08GZ32 Data Sheet, Rev. 3
188
Freescale Semiconductor