MC68HC08GZ32 Datasheet, PDF (29/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Unused ROM Locations
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
Register Name
Port A Data Register ^Read:
(PTA) Write:
See page 150. _Reset:
Port B Data Register ^Read:
(PTB) Write:
See page 153. _Reset:
Port C Data Register ^Read:
(PTC) Write:
See page 155. _Reset:
Port D Data Register ^Read:
(PTD) Write:
See page 157. _Reset:
Data Direction Register A ^Read:
(DDRA) Write:
See page 151. _Reset:
Data Direction Register B ^Read:
(DDRB) Write:
See page 154. _Reset:
Data Direction Register C ^Read:
(DDRC) Write:
See page 155. _Reset:
Data Direction Register D ^Read:
(DDRD) Write:
See page 158. _Reset:
Port E Data Register ^Read:
(PTE) Write:
See page 160. _Reset:
ESCI Prescaler Register ^Read:
(SCPSC) Write:
See page 191. _Reset:
ESCI Arbiter Control ^Read:
Register (SCIACTL) Write:
See page 195. _Reset:
ESCI Arbiter Data ^Read:
Register (SCIADAT) Write:
See page 196. _Reset:
Data Direction Register E ^Read:
(DDRE) Write:
See page 161. _Reset:
Bit 7
PTA7
PTB7
1
PTD7
DDRA7
0
DDRB7
0
0
0
DDRD7
0
0
PS2
0
AM1
0
ARD7
0
0
0
6
PTA6
5
PTA5
PTB6
PTB5
PTC6
PTC5
PTD6
PTD5
DDRA6
0
DDRB6
0
DDRC6
0
DDRD6
0
0
DDRA5
0
DDRB5
0
DDRC5
0
DDRD5
0
PTE5
PS1
PS0
0
0
ALOST
AM0
0
0
ARD6
ARD5
0
0
0
DDRE5
0
0
= Unimplemented
4
3
2
1
PTA4
PTA3
PTA2
PTA1
Unaffected by reset
PTB4
PTB3
PTB2
PTB1
Unaffected by reset
PTC4
PTC3
PTC2
PTC1
Unaffected by reset
PTD4
PTD3
PTD2
PTD1
Unaffected by reset
DDRA4 DDRA3 DDRA2 DDRA1
0
0
0
0
DDRB4 DDRB3 DDRB2 DDRB1
0
0
0
0
DDRC4 DDRC3 DDRC2 DDRC1
0
0
0
0
DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
PTE4
PTE3
PTE2
PTE1
Unaffected by reset
PSSB4 PSSB3 PSSB2 PSSB1
0
0
0
0
AFIN
ARUN AOVFL
ACLK
0
0
0
0
ARD4
ARD3
ARD2
ARD1
0
0
0
0
DDRE4 DDRE3 DDRE2 DDRE1
0
0
R = Reserved
0
0
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Bit 0
PTA0
PTB0
PTC0
PTD0
DDRA0
0
DDRB0
0
DDRC0
0
DDRD0
0
PTE0
PSSB0
0
ARD8
0
ARD0
0
DDRE0
0
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
29