MC68HC08GZ32 Datasheet, PDF (204/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
15.3.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at
least the minimum t_RL time and no other reset sources are present. Figure 15-5 shows the relative timing.
Table 15-2. PIN Bit Set Timing
Reset Type
POR/LVI
All others
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
CGMOUT
RST
IAB
PC
VECT H VECT L
Figure 15-5. External Reset Timing
15.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset continues to be asserted for an additional 32 cycles at which point
the reset vector will be fetched. See Figure 15-6. An internal reset can be caused by an illegal address,
illegal opcode, COP timeout, LVI, or POR. See Figure 15-7.
NOTE
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 15-6.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
RST
CGMXCLK
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
IAB
VECTOR HIGH
Figure 15-6. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
MODRST
Figure 15-7. Sources of Internal Reset
MC68HC08GZ32 Data Sheet, Rev. 3
204
Freescale Semiconductor