MC68HC08GZ32 Datasheet, PDF (205/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Reset and System Initialization
15.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set.
15.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR) if the COPD bit in the MOR1
register is cleared. The SIM actively pulls down the RST pin for all internal reset sources.
The COP module is disabled if the RST pin or the IRQ pin is held at V_TST while the MCU is in monitor
mode. During a break state, V_TST on the RST pin disables the COP module.
OSC1
PORRST
CGMXCLK
4096
CYCLES
32
CYCLES
32
CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 15-8. POR Recovery
15.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
205