MC68HC08GZ32 Datasheet, PDF (38/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map
Table 2-1. Vector Addresses (Continued)
Vector Priority
Highest
Vector
IF6
IF5
IF4
IF3
IF2
IF1
—
—
Address
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
Vector
TIM2 Channel 0 Vector (High)
TIM2 Channel 0 Vector (Low)
TIM1 Overflow Vector (High)
TIM1 Overflow Vector (Low)
TIM1 Channel 1 Vector (High)
TIM1 Channel 1 Vector (Low)
TIM1 Channel 0 Vector (High)
TIM1 Channel 0 Vector (Low)
PLL Vector (High)
PLL Vector (Low)
IRQ Vector (High)
IRQ Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
Reset Vector (Low)
2.6 Random-Access Memory (RAM)
The RAM locations are broken into two non-continuos memory blocks. The RAM addresses locations are
$0040–$043F and $0580–$097F. The location of the stack RAM is programmable. The 16-bit stack
pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently
access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
MC68HC08GZ32 Data Sheet, Rev. 3
38
Freescale Semiconductor