MC68HC08GZ32 Datasheet, PDF (180/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in
from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
14.4.3.8 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
• Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate ESCI error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the ESCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate ESCI error CPU interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects
a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate ESCI error
CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the ESCI detects a parity error in incoming
data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate ESCI error CPU
interrupt requests.
14.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
14.5.1 Wait Mode
The ESCI module remains active in wait mode. Any enabled CPU interrupt request from the ESCI module
can bring the MCU out of wait mode.
If ESCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
14.5.2 Stop Mode
The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states.
ESCI module operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission
or reception results in invalid data.
14.6 ESCI During Break Module Interrupts
The BCFE bit in the break flag control register (SBFCR) enables software to clear status bits during the
break state. See 20.2 Break Module (BRK).
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
MC68HC08GZ32 Data Sheet, Rev. 3
180
Freescale Semiconductor