MC68HC08GZ32 Datasheet, PDF(111/320 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC08GZ32 Datasheet, PDF (111/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Chapter 11

Low-Voltage Inhibit (LVI)

11.1 Introduction

This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin

and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.

11.2 Features

Features of the LVI module include:

â¢ Programmable LVI reset

â¢ Selectable LVI trip voltage

â¢ Programmable stop mode operation

11.3 Functional Description

Figure 11-1 shows the structure of the LVI module. The LVI module contains a bandgap reference circuit

and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage.

Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls

below a voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in

stop mode. The LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, VTRIPF, to be

configured for 5-V operation or 3-V operation. The actual trip points are shown in Chapter 21 Electrical

Specifications.

NOTE

After a power-on reset (POR) the LVI's default mode of operation is

whatever was selected in MOR1. In a 5-V system, select the LVI5OR3 bit

in MOR1 to be set (to select the 5-V trip point). In a 3-V system, select the

LVI5OR3 bit in MOR1 to be clear (to select the 3-V trip point). Regardless

of the selection chosen, care must be taken to ensure that VDD is above

the appropriate mode trip voltage after POR is released

LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the mask option register (MOR1). See Figure 5-2.

Mask Option Register 1 (MOR1) for details of the LVIâs configuration bits. Once an LVI reset occurs, the

MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See

15.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The

output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).

An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.

MC68HC08GZ32 Data Sheet, Rev. 3

Freescale Semiconductor

111

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