MC68HC08GZ32 Datasheet, PDF (151/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port A
AD15–AD8 — Analog-to-Digital Input Bits
AD15–AD8 are pins used for the input channels to the analog-to-digital converter module. The channel
select bits in the ADC status and control register define which port A pin will be used as an ADC input
and overrides any control from the port I/O logic by forcing that pin as the input to the analog circuitry.
NOTE
Care must be taken when reading port A while applying analog voltages to
AD15–AD8 pins. If the appropriate ADC channel is not enabled, excessive
current drain may occur if analog voltages are applied to the
PTAx/KBDx/ADx pin, while PTA is read as a digital input during the CPU
read cycle. Those ports not selected as analog input channels are
considered digital I/O ports.
13.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0004
Bit 7
6
5
4
3
2
1
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1
0
0
0
0
0
0
0
Figure 13-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA7–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA7–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 13-4 shows the port A I/O logic.
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-2 summarizes the operation of the port A pins.
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
151