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| MC68HC08GZ32 Datasheet, PDF (159/320 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDPUEx
Port D
VDD
INTERNAL
PULLUP
DEVICE
PTDx
READ PTD ($0003)
Figure 13-15. Port D I/O Circuit
Table 13-5. Port D Pin Functions
PTDPUE
Bit
1
0
X
DDRD
Bit
0
0
1
PTD
Bit
X(1)
X
X
I/O Pin
Mode
Input, VDD(2)
Input, Hi-Z(4)
Output
Accesses
to DDRD
Read/Write
DDRD7âDDRD0
DDRD7âDDRD0
DDRD7âDDRD0
1. X = Donât care
2. I/O pin pulled up to VDD by internal pullup device.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High imp[edance
Accesses
to PTD
Read
Write
Pin
PTD7âPTD0(3)
Pin
PTD7âPTD0(3)
PTD7âPTD0 PTD7âPTD0
13.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bitâs DDRD is configured for output mode.
Address: $000F
Bit 7
Read:
PTDPUE7
Write:
Reset: 0
6
PTDPUE6
0
5
PTDPUE5
0
4
PTDPUE4
0
3
PTDPUE3
0
2
PTDPUE2
0
1
PTDPUE1
0
Bit 0
PTDPUE0
0
Figure 13-16. Port D Input Pullup Enable Register (PTDPUE)
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
159
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