MC68HC08GZ32 Datasheet, PDF (263/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
the current counter overflow period. Writing a larger value in an output compare interrupt routine
(at the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
19.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
PTD6/T2CH0 pin. The TIM2 channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM2 channel 0 status and control register (T2SC0) links channel 0 and channel 1.
The output compare value in the TIM2 channel 0 registers initially controls the output on the PTD6/T2CH0
pin. Writing to the TIM2 channel 1 registers enables the TIM2 channel 1 registers to synchronously control
the output after the TIM2 overflows. At each subsequent overflow, the TIM2 channel registers (0 or 1) that
control the output are the ones written to last. T2SC0 controls and monitors the buffered output compare
function, and TIM2 channel 1 status and control register (T2SC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTD7/T2CH1, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the
PTF4/T2CH2 pin. The TIM2 channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM2 channel 2 status and control register (T2SC2) links channel 2 and channel 3.
The output compare value in the TIM2 channel 2 registers initially controls the output on the PTF4/T2CH2
pin. Writing to the TIM2 channel 3 registers enables the TIM2 channel 3 registers to synchronously control
the output after the TIM2 overflows. At each subsequent overflow, the TIM2 channel registers (2 or 3) that
control the output are the ones written to last. T2SC2 controls and monitors the buffered output compare
function, and TIM2 channel 3 status and control register (T2SC3) is unused. While the MS2B bit is set,
the channel 3 pin, PTF5/T2CH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the
PTF6/T2CH4 pin. The TIM2 channel registers of the linked pair alternately control the output.
Setting the MS4B bit in TIM2 channel 4 status and control register (T2SC4) links channel 4 and channel 5.
The output compare value in the TIM2 channel 4 registers initially controls the output on the PTF6/T2CH4
pin. Writing to the TIM2 channel 5 registers enables the TIM2 channel 5 registers to synchronously control
the output after the TIM2 overflows. At each subsequent overflow, the TIM2 channel registers (4 or 5) that
control the output are the ones written to last. T2SC4 controls and monitors the buffered output compare
function, and TIM2 channel 5 status and control register (T2SC5) is unused. While the MS4B bit is set,
the channel 5 pin, PTF7/T2CH5, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
19.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM2 can generate a PWM
signal. The value in the TIM2 counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM2 counter modulo registers. The time
between overflows is the period of the PWM signal.
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
263