MC68HC08GZ32 Datasheet, PDF (127/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock System
The previously described timer signal can be routed into the on-chip timer interface module (TIM). This
signal is connected to channel 0 of timer interface module 1 (TIM1) under the control of the timer link
enable (TLNKEN) bit in CMCR0.
After timer n has been programmed to capture rising edge events, it can be used under software control
to generate 16-bit time stamps which can be stored with the received message.
12.10 Clock System
Figure 12-8 shows the structure of the MSCAN08 clock generation circuitry and its interaction with the
clock generation module (CGM). With this flexible clocking scheme the MSCAN08 is able to handle CAN
bus rates ranging from 10 kbps up to 1 Mbps.
CGMXCLK
OSC
CGM
MSCAN08
÷2
PLL
CLKSRC
÷2
CGMOUT
(TO SIM)
BCS
÷2
(2 * BUS FREQUENCY)
PRESCALER
(1 ... 64)
MSCANCLK
Figure 12-8. Clocking Scheme
The clock source bit (CLKSRC) in the MSCAN08 module control register (CMCR1) (see 12.13.1
MSCAN08 Module Control Register 0) defines whether the MSCAN08 is connected to the output of the
crystal oscillator or to the PLL output.
The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of
the CAN protocol are met.
NOTE
If the system clock is generated from a PLL, it is recommended to select the
crystal clock source rather than the system clock source due to jitter
considerations, especially at faster CAN bus rates.
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
127