MC68HC08GZ32 Datasheet, PDF (279/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

ADDRESS BUS[15:8]
Break Module (BRK)
ADDRESS BUS[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BKPT
(TO SIM)
ADDRESS BUS[7:0]
Figure 20-2. Break Module Block Diagram
Addr.
Register Name
$FE00
Break Status Register ^Read:
(BSR) Write:
See page 281. _Reset:
$FE03
Break Flag Control ^Read:
Register (BFCR) Write:
See page 282. _Reset:
$FE09
Break Address High ^Read:
Register (BRKH) Write:
See page 281. _Reset:
$FE0A
Break Address Low ^Read:
Register (BRKL) Write:
See page 281. _Reset:
$FE0B
Break Status and Control ^Read:
Register (BRKSCR) Write:
See page 280. _Reset:
1. Writing a 0 clears SBSW.
Bit 7
R
BCFE
0
Bit15
0
Bit 7
0
BRKE
0
6
5
R
R
R
R
Bit14
Bit13
0
0
Bit 6
Bit 5
0
0
0
BRKA
0
0
= Unimplemented
4
3
2
1
Bit 0
SBSW
R
R
R
Note⁽¹⁾
R
0
R
R
R
R
R
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R = Reserved
Figure 20-3. Break I/O Register Summary
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
279