MC68HC08GZ32 Datasheet, PDF (285/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor Module (MON)
Table 20-1. Monitor Mode Signal Requirements and Options
Mode
Serial
Communi-
IRQ
RST
Reset
Vector
cation
Mode
Selection
Divider
PLL
PTA0 PTA1 PTB0 PTB1 PTB4
COP
Communication
Speed
Comments
External Bus Baud
Clock Frequency Rate
—
X GND X
XX X
X
XX
X
X
X
X
Reset
condition
V_DD
V_TST or
X
1
0
1
0
Monitor
V_TST
V_DD
V_TST or
X
1
0
1
0
V_TST
0 OFF Disabled 4.0 MHz 2.0 MHz 7200
1 OFF Disabled 8.0 MHz 2.0 MHz 7200
V_DD V_DD Not
User or or $FF X X
X
X
GND V_TST
X X Enabled X
X
X
MON08
Function
[Pin No.]
V_TST
[6]
RST
[4]
—
COM SSEL MOD0 MOD1 DIV4
[8] [10] [12] [14] [16]
—
—
OSC1
[13]
—
—
1. PTA0 must have a pullup resistor to V_DD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 7200. Baud rate using external oscillator is bus
frequency / 278.
3. External clock is an 4.0 MHz or 8.0 MHz crystal on OSC1 and OSC2 or a canned oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC
NC
NC
NC
NC
NC
OSC1
V_DD
1
2 GND
3
4 RST
5
6 IRQ
7
8 PTA0
9 10 PTA1
11 12 PTB0
13 14 PTB1
15 16 PTB4
20.3.1.1 Monitor Mode
If V_TST is applied to IRQ and PTB4 is low upon monitor mode entry, the bus frequency is a divide-by-two
of the input clock. If PTB4 is high with V_TST applied to IRQ upon monitor mode entry, the bus frequency
will be a divide-by-four of the input clock. Holding the PTB4 pin low when entering monitor mode causes
a bypass of a divide-by-two stage at the oscillator only if V_TST is applied to IRQ. In this event, the
CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
285