MC68HC08GZ32 Datasheet, PDF (112/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
V_DD
LVIPWRD
FROM MOR1
STOP INSTRUCTION
FROM MOR1
LVIRSTD
LVISTOP
FROM MOR1
LOW V_DD
DETECTOR
V_DD > LVI_Trip = 0
V_DD ≤ LVI_Trip = 1
LVI5OR3
FROM MOR1
LVIOUT
Figure 11-1. LVI Module Block Diagram
LVI RESET
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
LVI Status Register ^{Read: LVIOUT}
0
0
0
0
0
0
0
$FE0C
(LVISR) Write:
See page 113. _Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. LVI I/O Register Summary
11.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level, software can monitor V_DD by polling
the LVIOUT bit. In the mask option register, the LVIPWRD bit must be at 0 to enable the LVI module, and
the LVIRSTD bit must be at 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls below the V_TRIPF level. In the mask option register, the
LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.
11.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF), the LVI will maintain a reset condition until
V_DD rises above the rising trip point voltage, V_TRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to V_TRIPF. V_TRIPR is greater than
V_TRIPF by the hysteresis voltage, V_HYS.
MC68HC08GZ32 Data Sheet, Rev. 3
112
Freescale Semiconductor