MC68HC08GZ32 Datasheet, PDF (137/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmer’s Model of Control Registers
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number of time quanta (T_q) clock cycles
by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 12-6).
Table 12-6. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization
Jump Width
1 T_q cycle
2 T_q cycle
3 T_q cycle
4 T_q cycle
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (T_q) clock, which is used to build up the individual bit timing,
according to Table 12-7.
.
Table 12-7. Baud Rate Prescaler
BRP5
0
0
0
0
:
:
1
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler
Value (P)
1
2
3
4
:
:
64
NOTE
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
12.13.4 MSCAN08 Bus Timing Register 1
Address: $0503
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SAMP
Write:
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Reset: 0
0
0
0
0
0
0
0
Figure 12-19. Bus Timing Register 1 (CBTR1)
SAMP — Sampling
This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per
bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit.
1 = Three samples per bit⁽¹⁾
0 = One sample per bit
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
137