MC68HC08GZ32 Datasheet, PDF (208/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
FROM RESET
I BBIRTESAEKT?
YES
INTERRUPT?
NO
YES
I BIT SET?
NO
IRQ
YES
INTERRUPT?
NO
AS MANY INTERRUPTS
AS EXIST ON CHIP
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
SWI
YES
INSTRUCTION?
NO
RTI
YES
INSTRUCTION?
NO
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 15-11. Interrupt Processing
15.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 15-12 demonstrates what happens when two interrupts are pending. If an interrupt
MC68HC08GZ32 Data Sheet, Rev. 3
208
Freescale Semiconductor