MC68HC08GZ32 Datasheet, PDF (130/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN08 Controller (MSCAN08)
12.12 Programmer’s Model of Message Storage
This section details the organization of the receive and transmit message buffers and the associated
control registers. For reasons of programmer interface simplification, the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a
13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit
buffers.
Addr⁽¹⁾
$05b0
Register Name
IDENTIFIER REGISTER 0
$05b1
IDENTIFIER REGISTER 1
$05b2
$05b3
IDENTIFIER REGISTER 2
IDENTIFIER REGISTER 3
$05b4
DATA SEGMENT REGISTER 0
$05b5
$05b6
DATA SEGMENT REGISTER 1
DATA SEGMENT REGISTER 2
$05b7
DATA SEGMENT REGISTER 3
$05b8
$05b9
DATA SEGMENT REGISTER 4
DATA SEGMENT REGISTER 5
$05bA
DATA SEGMENT REGISTER 6
$05bB
$05bC
$05bD
DATA SEGMENT REGISTER 7
DATA LENGTH REGISTER
TRANSMIT BUFFER PRIORITY REGISTER⁽²⁾
$05bE
$05bF
UNUSED
UNUSED
1. Where b equals the following:
b = 4 for receive buffer
b = 5 for transmit buffer 0
b = 6 for transmit buffer 1
b = 7 for transmit buffer 2
2. Not applicable for receive buffers
Figure 12-11. Message Buffer Organization
12.12.1 Message Buffer Outline
Figure 12-12 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 12-13. All bits of
the 13-byte data structure are undefined out of reset.
NOTE
The foreground receive buffer can be read anytime but cannot be written.
The transmit buffers can be read or written anytime.
MC68HC08GZ32 Data Sheet, Rev. 3
130
Freescale Semiconductor