MC68HC08GZ32 Datasheet, PDF (201/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

STOP/WAIT
CONTROL
SIM
COUNTER
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
CGMXCLK (FROM CGM)
Introduction
CGMOUT (FROM CGM)
÷2
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
FORCED MONITOR MODE ENTRY
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 15-2. SIM Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
SIM Break Status Register ^Read:
R
$FE00
(SBSR) Write:
R
R
R
R
SBSW
R
Note⁽¹⁾
R
See page 215. _Reset:
0
0
0
0
0
0
0
0
1. Writing a 0 clears SBSW.
SIM Reset Status Register ^{Read: POR}
PIN
COP
ILOP
ILAD MODRST LVI
0
$FE01
(SRSR) Write:
See page 215. _POR:
1
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 15-3. SIM I/O Register Summary
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
201