MC68HC08GZ32 Datasheet, PDF (261/320 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
Addr.
$0458
$0459
$045A
$045B
$045C
$045D
$045E
$045F
$0460
$0461
Register Name
TIM2 Channel 2 Register Low ^Read:
(T2CH2L) Write:
See page 274. _Reset:
TIM2 Channel 3 Status and ^Read:
Control Register (T2SC3) Write:
See page 271. _Reset:
TIM2 Channel 3 Register High ^Read:
(T2CH3H) Write:
See page 274. _Reset:
TIM2 Channel 3 Register Low ^Read:
(T2CH3L Write:
See page 274.) _Reset:
TIM2 Channel 4 Status and ^Read:
Control Register (T2SC4) Write:
See page 271. _Reset:
TIM2 Channel 4 Register High ^Read:
(T2CH4H) Write:
See page 274. _Reset:
TIM2 Channel 4 Register Low ^Read:
(T2CH4L) Write:
See page 274. _Reset:
TIM2 Channel 5 Status and ^Read:
Control Register (T2SC5) Write:
See page 271. _Reset:
TIM2 Channel 5 Register High ^Read:
(T2CH5H) Write:
See page 274. _Reset:
TIM2 Channel 5 Register Low ^Read:
(T2CH5L) Write:
See page 274. _Reset:
Bit 7
Bit 7
CH3F
0
0
Bit 15
Bit 7
CH4F
0
0
Bit 15
Bit 7
CH5F
0
0
Bit 15
Bit 7
6
5
6
5
0
CH3IE
0
0
14
13
6
5
0
CH4IE
0
0
14
13
6
5
0
CH5IE
0
0
14
13
6
5
= Unimplemented
4
3
2
4
3
2
Indeterminate after reset
MS3A ELS3B ELS3A
0
0
0
12
11
10
Indeterminate after reset
4
3
2
Indeterminate after reset
MS4A ELS4B ELS4A
0
0
0
12
11
10
Indeterminate after reset
4
3
2
Indeterminate after reset
MS5A ELS5B ELS5A
0
0
0
12
11
10
Indeterminate after reset
4
3
2
Indeterminate after reset
Figure 19-3. TIM2 I/O Register Summary (Sheet 2 of 2)
1
Bit 0
1
Bit 0
TOV3 CH3MAX
0
0
9
Bit 8
1
Bit 0
TOV4 CH4MAX
0
0
9
Bit 8
1
Bit 0
TOV5 CH5MAX
0
0
9
Bit 8
1
Bit 0
19.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in T2SC0 through T2SC5
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIM2 latches the contents of the TIM2 counter into the TIM2 channel
registers, T2CHxH:T2CHxL. Input captures can generate TIM2 CPU interrupt requests. Software can
MC68HC08GZ32 Data Sheet, Rev. 3
Freescale Semiconductor
261